ECE 6745
Last Updated
- Schedule of Classes - September 22, 2025 1:06PM EDT
Classes
ECE 6745
Course Description
Course information provided by the 2025-2026 Catalog.
Principles and practices involved in the design, implementation, testing, and evaluation of complex standard-cell ASIC chips using automated state-of-the-art CAD tools. Topics include hardware description languages; CMOS logic, state, and interconnect fundamentals; chip design methodologies; automated cell-based design; CAD algorithms; details of accurately modeling ASIC delay, energy, and area; robustness issues; testing, verification, and debugging; power distribution and clocking; packaging and I/O. Includes a six-week open ended project where small groups of students design, implement, test, and evaluate an interesting technique in computer architecture using functional-, microarchitectural-, registertransfer-, and layout-level modeling.
Prerequisites ECE 4750.
Last 4 Terms Offered 2025SP, 2023SP, 2022SP, 2021SP
Regular Academic Session. Choose one lecture and one discussion.
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Credits and Grading Basis
4 Credits Graded(Letter grades only)
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Class Number & Section Details
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Meeting Pattern
- TR
- Jan 20 - May 5, 2026
Instructors
Batten, C
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Additional Information
Instruction Mode: In Person
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